Union Minister of State for Skill Development & Entrepreneurship and Electronics & IT Rajeev Chandrasekhar (File pic/PTI)
The Digital India RISC-V (DIR-V) programme represents an enormous alternative for the startups within the design ecosystem in India to construct the following technology of chips round RISC V processors and methods round DIR V units, stated Rajeev Chandrasekhar
Union Minister of State for Skill Development & Entrepreneurship and Electronics & IT Rajeev Chandrasekhar inaugurated the Nationwide Roadshow on Digital India RISC-V (DIR-V) programme, heralding a pivotal second in India’s technological development. This collaborative effort between C-DAC, IEEE India Council, and the Ministry of Electronics & IT attracted world leaders within the RISC-V design realm.
Chandrasekhar highlighted the event, saying: “This is a significant milestone and tremendous progress that today we are able to demonstrate to the entire country the capabilities not just in broad chip design but in terms of high-performance chip design in RISC V domain.”
Underlining the federal government’s dedication, Chandrasekhar careworn, “The opportunities created in the last 7 years by PM Narendra Modi’s policies represent an unprecedented opportunity for success and growth…Our primary focus is to grow the RISC V and DIR V ecosystems.”
Expressing India’s ambition within the technological panorama, he acknowledged: “It is certainly our ambition as a country and with hundreds and thousands of engineers amongst the audience that we will master and become if not the global leader but certainly amongst the world’s leading nations in propagating and navigating the capabilities and capacities to create innovation around the RISC V and DIR V family of chips and systems.”
Acknowledging the burgeoning startup ecosystem, Chandrasekhar emphasised that the DIR V ecosystem has seen many startups comparable to Ventana Micro Systems, Esperanto Technologies, InCore Semiconductors, Mindgrove Technologies, and Morphing Machines. According to him, the programme represents an enormous alternative for the startups within the design ecosystem in India to construct the following technology of chips round RISC V processors and methods round DIR V units.
Highlighting future utility areas, he identified: “While RISC V has always represented open source and collaborative framework for innovation in semiconductor design and fabless design, today with the growing need for AI and machine learning DIR V will also be able to address high-performance computing and applications in the coming years.”
The nationwide roadshow goals to equip 1,500 contributors with complete insights into DIR-V VEGA processors and their ecosystem. Hands-on classes, endorsed by world leaders like Prof Krste Asanovic and Calista Redmond, will empower contributors from 15 tutorial establishments throughout India.
